1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to techniques for debugging integrated circuits.
2. Description of the Prior Art
It is known to provide integrated circuits with debug mechanisms. Some known debug mechanisms provide the ability to generate memory transactions to read or write memory locations within the memory address space of an integrated circuit. These debug mechanisms can accordingly act as a transaction master and can be useful in reading data to determine the state of the integrated circuit and writing data to provide a desired stimulus to the integrated circuit.
It is typically the case that the number of connection pins provided to an integrated circuit to support debug operations is low. The rate of increase in pins on integrated circuit packages has not kept apace with the rate of increase in complexity of those circuits (the so-called Moore's Law). There is considerable pressure to use connection pins to an integrated circuit for other functions. The debug operations may only be used during development and accordingly it is difficult to justify dedicating many connection pins to debug functions. This has the consequence of restricting the bandwidth with which a debug controller may communicate with debug circuitry upon an integrated circuit to instruct transactions such as memory reads and memory writes to be performed. A typical integrated circuit may be operating at a frequency of the order of gigahertz whereas a debug interface may only be able to communicate at a frequency of a few megahertz. This mismatch in speed limits the way in which debug initiated transactions may be combined with other transactions which are occurring at full speed within the integrated circuit.
In order to increase the usefulness of the debug mechanisms provided for integrated circuits, it is desirable to increase the rate at which debug operations can be performed while not increasing, or preferably reducing, the number of pins dedicated to debug. One way to achieve this is to increase the bandwidth with which the debug controller may communicate via the debug interface with the integrated circuit. Advances in serial data communication technology, such as advances in USB-type communication, have the result that it is becoming possible to communicate with the debug mechanisms upon an integrated circuit on timescales more comparable with the timescales upon which the integrated circuit internally performs its data processing operations, without increasing the debug pin count.
A further option is to enhance the debug circuitry within the integrated circuit. More complex debug circuitry enabled by increasing levels of integration mean that comparatively simple commands sent by the debug controller over the debug interface can be converted into complex transactions, e.g. repetitive actions such as block memory fill. Operations can also be buffered by the debug circuitry, so that the debugger does not need to poll the debug interface and wait for one operation to complete before sending further operations. Both options can be combined.